Forth Sequencer

The sequencer is based on the J1 forth CPU, by James Bowman. This is a very simple 16 instruction core.

The native RAM blocks inside the Artix7 FPGA are 18 bits wide, so I extended the J1 CPU to 18 bits wide, to provide more code space and wider instructions.

The extra instruction space is used to drive the SIMD bit-serial CPUs. This means SIMD instructions can be mixed freely with J1 instructions. The finished code will have long strings of SIMD instructions with basic loop control and host interaction using J1 instructions.

The initial system load for the J1 comes from the same Flash storage used to hold the FPGA configuration. It also holds forth pages - blocks of forth that can be loaded on demand.

For development purposes, it has a serial console, where forth can be used interactively.

The forth will probably disappear over time - to be replaced with fixed blocks of SIMD code - for now it is just a great way to experiment on the hardware.